Currently the NPN bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process usually use heavy doped collector buried layer to reduce the collector resistance. This process needs high temperature and long time furnace drive-in to make the dopant to diffuse deeper and decrease the capacitance between buried layer and silicon substrate. This process also need n-type heavy implanting (above 1e15 cm−2) to realize n-type buried layer connection and form collector pick-up. The epitaxy layer on the collector buried layer forms the collector. The p-type doped Silicon or SiGe (Silicon Germanium) epitaxy forms the base and the heavy doped polysilicon forms the emitter. The isolation between two transistors is through deep trench isolation process. The existing parasitic PNP bipolar transistor design in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process has the very mature and reliable process, but also comes with the disadvantages as below: 1. buried layer needs high temperature and long time furnace drive-in; 2. high cost of collector epitaxy; 3. process complication and high cost of deep trench isolation.